The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, arc neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Error-containment logic, such as hardware or firmware configured with Live Error Recovery (“LER”) technology developed by Intel® Corporation of Santa Clara, Calif., may be used to contain errors that occur on input/output (“I/O”) devices operably coupled using various technologies, such as Peripheral Component Interconnect Express (“PCIe”), LER enables recovery of an I/O device/port after an error on the port is contained. However, there still may be system failure, e.g., at an operating system (“OS”) or a virtual machine monitor (“VMM”) level, because there may be insufficient or no coordination between the error-containment logic and the OS/VMM.